The present invention relates to a highly integrated semiconductor device, more particularly, to a fuse within a highly integrated semiconductor device that is capable of determining whether to transfer an electronic signal or connect two different terminals.
A fuse is generally used in many electrical and electronic devices. In a normal condition, the fuse allows current to flow in the circuit. However, when the fuse is cut in the overcurrent condition, the fuse permanently makes whole or partial of the circuit shut off. Unlike a is switch, the fuse cannot be used for temporarily turning on or off current flow in a circuit.
A semiconductor device is made to perform a specific operation by a fabrication process including injecting an impure material and depositing conductive and nonconductive materials onto a predetermined area of a wafer mounted in a chamber. One example of the semiconductor device is a semiconductor memory device. The semiconductor memory device includes plural components or elements such as a transistor, a capacitor, a resistor, a fuse, and etc. Herein, the capacitor is mainly used for temporarily storing data, and the fuse is used in a redundancy circuit or a power supply circuit of the semiconductor memory.
The redundancy circuit using the fuse for permanently storing address of a defective cell (or unit cell) replaces the defective unit cell with a spare cell in order to prevent the semiconductor memory device having a minor defect from being treated as a defective product, thereby increasing the yield. Recently, a memory chip density of the semiconductor memory device increases. When few unit cells in the semiconductor memory device are defective, destroying the semiconductor memory device including few defective cells can be ineffective and result in a reduced yield because a ratio of normal cells to defective cells in the semiconductor memory device is likely to be very low. Thus, when detecting any defective unit cell during manufacturing and testing process of the semiconductor memory device, the redundancy circuit replaces the defective unit cell with a redundant memory cell in a repair process in order to secure a higher yield for semiconductor devices having a plurality of unit cells.
When a particular unit cell of the semiconductor memory device is defective, a repair process for substituting the defective unit cell with a spare cell is performed. Namely, an address for accessing the defective unit cell is inputted externally. The repair process is performed in which the address of the defective unit cell is stored to prevent the defective cell from being accessed, and allow another cell to be accessed in place of the defective cell. The fuse is the most commonly used device among those that are used to store the address of the defective unit cell during the repair process. An electronic connection is permanently disabled by applying a laser beam to a target fuse in the semiconductor device, and the address of the defective unit cell can be permanently stored (or programmed) by such a fuse blowing operation.
During a fabricating process of the semiconductor memory device including a plurality of unit cells before the fabrication process of the semiconductor memory device is completed, it is difficult to know which cells among the plurality of unit cells would become defective, i.e., the location or address of a defective cell. Accordingly, a fuse box having a plurality of fuses can be additionally implemented in the semiconductor memory device in order to substitute a normal spare cell for the defective unit cell located in any area of the memory chip.
As the data storage capacity of a semiconductor memory device is increased, the semiconductor memory device is provided with an is increased number of unit cells as well as an increased number of fuses for substituting the defective unit cell with an extra unit cell. However, as the semiconductor memory device is required to have a decreased chip size, the semiconductor memory device needs to have a high integration density. As described above, laser is selectively applied to physically blow a portion of the fuses and therefore. In order not to affect fuses adjacent to the targeted fuse, a sufficient spacing between adjacent fuses should be provided. However, this hinders the obtaining of a high integration density of the semiconductor memory device.
FIGS. 1a and 1b are respectively a circuit diagram and a plan view illustrating a fuse arrangement (or fuse block) in a semiconductor device according to the related art.
Referring to FIG. 1a, a first fuse block 100 and a second fuse block 150 respectively include a plurality of fuses F1 through F4 coupled between a power supply voltage VDD and a ground voltage VSS, switching elements PT and NT for controlling a coupling between the power supply voltage VDD and the ground voltage VSS, and control units N1 through N4 that are controlled by fuse control signals, <B>, <C>, <D>, <E> for the first fuse block 100 and <2>, <3>, <4>, <5> for the second fuse block 150, to allow current to flow depending on conditions of the fuses F1 through F4. Here, if the fuse blocks 100 and 150 are employed in the redundancy circuit, the fuse blocks 100 and 150 are used to store an address of a unit cell of different banks.
An operation of identifying the condition of the fuses F1 to F4 of the first and the second fuse blocks 100 and 150 will be briefly discussed with reference to the circuit diagram of FIG. 1a. In order to determine if a first fuse F1 of the first fuse block 100 blows, a first fuse control signal <B> corresponding to the first fuse F1 is activated such that current flows through a first control unit N1, wherein other fuse control signals <C>, <D> and <E> are inactivated (or not applied) such that current only flows along a path that passes through the first fuse F1. Next, the switching elements PT and NT are activated to connect the fuse with the power supply voltage VDD and the ground voltage VSS. If the first fuse F1 is blown, current does not flow through the first fuse block 100. Otherwise, current flows through the first fuse block 100. In this manner, it is determined whether the first fuse F1 is blown or not.
The four fuses F1 to F4 in the fuse blocks 100 and 150 form, two by two, a Y-shaped fuse pattern. Specifically, the first fuse block 100 includes a first fuse pair 110 and a second fuse pair 120, each of which includes two adjacent fuses. The second block 150 includes a third fuse pair 160 and a fourth fuse pair 170, each of which includes two adjacent fuses.
Referring to FIG. 1b, the first through fourth fuse pairs 110, 120, 160 and 170 shown in FIG. 1a are not arranged in parallel but are arranged to form a Y pattern or an upside down Y pattern, wherein the Y pattern and the upside down Y pattern are arranged alternating with one another. Such structure and arrangement may reduce the size of an area to be occupied by the fuse box. However, in the semiconductor is device having an increased integration density, it becomes difficult to form a diagonal line pattern of the Y-shaped pattern due to limitation of patterning techniques.
FIG. 2 is a picture demonstrating a problem of the fuse of FIGS. 1a and 1b. 
As shown in FIG. 2, a plurality of the fuses are arranged in a Y shaped pattern or an upside down Y shaped pattern and a portion of the diagonal lines of respective Y or upside down Y shaped patterns are damaged.
Specifically, when patterning the Y shaped fuse after an electrically conducting material is mounted, in case of a straight line pattern, it is easy to secure a manufacturing margin so that a required width of a designed pattern can be implemented. However, in case of a diagonal line pattern, if an exposure time is increased in order to secure the width of the pattern, the diagonal line pattern may be connected with adjacent patterns. Therefore, in order to avoid this, the Y shaped pattern is configured to have a thin width in contrast to the straight line pattern during a lithography process using a mask. When the fuse has a thin width, the resistance of the fuse is increased so that current flowing through the fuse may not be detected due to high resistance thereof, which causes an erroneous operation of the semiconductor device.
In addition, as the manufacture margin is reduced due to a high integration density, the diagonal line pattern having a thin width can be cut off. If the diagonal line pattern is cut off, the fuse becomes inoperable regardless of whether the straight line pattern blows. Particularly, when the fuse used in the redundancy circuit of the semiconductor memory device is cut off, the semiconductor memory device cannot remember the address of the defective unit cell so that the defective unit cell cannot be repaired. In this case, the yield of the semiconductor memory device is greatly decreased.